1. Field of the Invention
The invention relates to a decoder circuit for an integrated monolithic static random access memory, which circuit is formed by a logic NOR-gate (P1) comprising a row of field effect transistors whose gate electrodes receive the n coded memory address signals or the complements thereof, the sources thereof being connected to ground whilst their drains are interconnected and constitute the output of the NOR-gate (P1) which is connected to a supply terminal (V.sub.DD1) via a load and which is connected to the gate electrode of a transistor of an output inverter stage.
2. Description of the Related Art
Memory circuits are virtually always organized in form of a network of cells which exhibits the structure of a matrix. Each cell, corresponding to a bit (=binary digit), is situated at the intersection of two lines, a horizontal line or row and a vertical line or column. These lines correspond to the memory addresses and are generally denoted as X.sub.1, X.sub.2 . . . , X.sub.n for the rows and Y.sub.1, Y.sub.2 . . . , Y.sub.n for the columns. Each cell of the memory thus has a unique address and can be selected by the simultaneous activation of the appropriate row and column. After selection of the cell, the data can be applied to the cell or be extracted from the cell via a pair of lines which are common to all cells and which are referred to as bit lines.
From the publication of M. Ino et al (Musashino Electrical Communication Laboratory) in the Proceedings "IEEE GaAs I.C. Symposium 1982", entitled "GaAs 1 Kb Static RAM with E/D MESFET DCFL", it is known to form a decoder circuit for a static RAM which is integrated in monolithic form on a gallium arsenide (GaAs) substrate and which is composed of field effect transistors (MESFET: Metal Semiconductor Field Effect Transistor). A decoder circuit as described in said document and illustrated in FIG. 1 on page 4 of this document is composed of elementary decoder circuits. Each elementary decoder is essentially formed by a NOR-gate which comprises n inputs, each of which is intended to receive one of the binary coded address inputs a.sub.1, a.sub.2, . . . , a.sub.n, expressed in the form of a true signal or the complement thereof and formed before being input into the decoder by an intermediate circuit (ADDRESS BUFFER) in order to obtain on the output of the NOR-gate a combination of bits which are produced by the logic NOR-function and which constitute the address of a row or a column.
This NOR-gate is formed by enhancement-type gallium arsenide field effect transistors with a pinch off voltage V.sub.T .gtoreq.0, which means that they are conductive only when the voltage applied to the gate electrode exceeds this voltage V.sub.T. The transistors forming this NOR-gate are connected in parallel, their common source being connected to ground whilst their common drain is connected to the shortcircuited gate-source of a depletion transistor which is used as said active load.
When the values of the output signal of the NOR-gate change from 0 to 1 or from 1 to 0, the associated voltage charges or discharges the output capacitance of the circuit. In order to achieve equivalent charging and discharging periods of this capacitance, the output signal of the NOR-gate is applied to the input of an inverter stage so that the true output signal and its complement become simultaneously available, after which these signals are applied to respective ones of the two inputs of a pushpull stage. The inverter stage used comprises an enhancement-type transistor as the inverter transistor and a depletion transistor as the load. The pushpull stage also comprises an enhancement-type transistor which is connected to ground in common source arrangement, in series with a depletion transistor which is connected to the supply voltage in common drain arrangement.
For the decoder circuit, it is desirable, for example, te replace the depletion transistors forming the active loads by resistive loads since they are easier to realize from a technological point of view. Also, it is desirable to replace the depletion transistor of the pushpull stage by an enhancement-type transistor so that only a single type of transistor will be required for manufacture of such a circuit.
However, when a simple transposition of the circuit described in said document is attempted as proposed above, immediately the following problem is encountered: between the output of the NOR-gate and ground a parasitic diode appears due to the fact that the inverter transistor to which the output voltage is applied is of the Schottky type. This parasitic diode prevents the output signal of the NOR-gate from reaching a sufficiently high level to unblock the transistor of the pushpull stage to which the output signal is applied. The pushpull stage is thus rendered ineffective, and in these circumstances the charging of the output capacitance of the elementary decoder will be difficult and time-consuming.